1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device having memory cells constituted by non-volatile transistors.
2. Description of the Related Art
In a non-volatile semiconductor memory device (e.g., an EPROM or E.sup.2 PROM) using a non-volatile transistor having a floating gate, occurrence of a change in threshold value of the memory cell transistor, which is called soft write, is known. It is known that this soft write has various modes. Typical soft write modes are a hot electron mode and a lucky electron mode.
In a conventional non-volatile semiconductor memory device, since only soft write in the hot electron mode receives attention, occurrence of soft write is prevented by setting a drain voltage of a memory cell at a value of about 2 V.
In recent years, however, it has been found that soft write occurs even when the drain voltage of the memory cell is set at about 2 V. It is also found that the soft write is caused by the above lucky electron mode.